1. Field of the Invention
The present invention relates to a data driver, an organic light emitting display, and a method of driving the same. More particularly, the present invention relates to a data driver having an enhanced driving speed, an organic light emitting display, and a method of driving the same.
2. Description of the Related Art
Various flat panel display devices having reduced weight and volume compared to cathode ray tubes (CRTs) have been developed. These flat panel display devices include, e.g., a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, etc. These exemplary displays operate differently to display an image.
For example, an organic light emitting display may display an image by using an organic light emitting diode that generates light by recombining electrons and holes. During operation, the organic light emitting display may supply a current corresponding to a data signal to organic light emitting diodes by employing driving, thin film transistors formed at each pixel so light may be emitted from the organic light emitting diodes. The organic light emitting display may offer certain advantages, since it may be operated with low power consumption and may provide a rapid response speed.
The organic light emitting display may generate data signals by using data supplied from an external source. The organic light emitting display may supply the generated data signals to pixels and display an image of desired brightness. A data driver for converting the data supplied from the external source into the data signals has been considered.
The data driver may include a data signal generator for converting the external data into the data signals. The data signal generator may include a digital-to-analog converter (hereinafter, referred to as “DAC”). The DAC may be positioned in each channel and may convert the data into the data signals. For example, the data signal generator may include first DACs generating voltages depending on the values of the upper bits of the data and second DACs for generating voltages depending on the values of the lower bits of the data.
FIG. 1 illustrates a circuit diagram of a conventional second DAC. Referring to FIG. 1, the second DAC 2 may receive a first reference voltage (ref1) and a second reference voltage (ref2) from a first DAC (not illustrated). The first DAC may receive a plurality of reference voltages from an external source. The first DAC may select the first reference voltage (ref1) and the second reference voltage (ref2) among the plurality of reference voltages received depending on a value of the upper bits of the data. The first DAC may supply the selected first and second reference voltages (ref1) and (ref2) to the second DAC 2 via a tenth switch SW10 and an eleventh switch SW11, as illustrated in FIG. 1. The tenth switch SW10 or the eleventh switch SW11 may be turned on depending on the value of the upper bits of the data. For the sake of discussion, assume that the first reference voltage (ref1) is lower than the second reference voltage (ref2).
The second DAC 2 may include a plurality of voltage dividing resistors R1 to R7 for dividing the voltage values of the first reference voltage (ref1) and the second reference voltage (ref2). The second DAC 2 may also include a plurality of switches SW1 to SW8 for supplying voltages divided from the voltage dividing resistors R1 to R7 to an output terminal (out).
A tenth resistor R10 may be arranged between the eleventh switch SW11 and the seventh resistor R7. The tenth resistor R10 may compensate for the switch resistances of the tenth switch SW10 and the eleventh switch SW11, so that the second DAC 2 may evenly divide the reference voltages via the voltage dividing resistors R1 to R7. That is, the resistance of the tenth resistor R10 may be calculated by summing the switch resistance value (i.e., a turn-on resistance value) of the tenth switch SW10 and the switch resistance value of the eleventh switch SW11. The tenth resistor R10 may have a resistance approximate to the resistance of the seventh resistor R7.
The voltage dividing resistors R1 to R7 may be arranged in series. The voltage dividing resistors R1 to R7 may evenly divide the first reference voltage (ref1) and the second reference voltage (ref2). In this regard, the resistance of each of the voltage dividing resistors R1 to R7 may be identical. Further, although FIG. 1 illustrates seven voltage dividing resistors R1 to R7, and assumes that the number of bits of the lower bits of the data is 3, the number of voltage dividing resistors may be different depending on the number of bits of the lower bits of the data.
The switches SW1 to SW8 may be arranged to supply the voltages divided by the voltage dividing resistors R1 to R7 to the output terminal (out). In particular, the first switch SW1 may be arranged between a first node N1 and the output terminal (out) to supply the second reference voltage (ref2) to the output terminal (out). The second switch SW2 may be arranged between a second node N2 and the output terminal (out) to supply the voltage value of the second node N2 to the output terminal (out). The third switch SW3 may be arranged between a third node N3 and the output terminal (out) to supply the voltage value of the third node N3 to the output terminal (out). The fourth switch SW4 may be arranged between a fourth node N4 and the output terminal (out) to supply the voltage value of the fourth node N4 to the output terminal (out). The fifth switch SW5 may be arranged between a fifth node N5 and the output terminal (out) to supply the voltage value of the fifth node N5 to the output terminal (out). The sixth switch SW6 may be arranged between a sixth node N6 and the output terminal (out) to supply the voltage value of the sixth node N6 to the output terminal (out). The seventh switch SW7 may be arranged between a seventh node N7 and the output terminal (out) to supply the voltage value of the seventh node N7 to the output terminal (out). The eighth switch SW8 may be arranged between an eighth node N8 and the output terminal (out) to supply the first reference voltage (ref1) to the output terminal (out).
One of the switches SW1 to SW8 may be turned on depending on the lower bits of the data. That is, any one of the switches SW1 to SW8 may be turned on depending on the value of the lower bits of the data, and a predetermined voltage may be supplied to the output terminal (out). The predetermined voltage supplied to the output terminal (out) may be supplied to pixels as a data signal.
However, in the organic light emitting display illustrated in FIG. 1, the predetermined voltage supplied to the output terminal (out) of the second DAC 2 is generated based on a reference voltage being supplied through at least one voltage dividing resistor and one switch. Therefore, the driving speed of the second DAC 2 may be significantly reduced. In other words, since the predetermined voltage is generated via the voltage dividing resistors R1 to R7, a period of time is required before voltages corresponding to the data signals may be supplied to the pixels. This additional time period may result in a driving speed that is undesirably low.
Additionally, it is preferable that the voltages corresponding to the data signals be charged in the pixels within one horizontal period. However, in the case that voltages corresponding to data signals are supplied via the voltage dividing resistors R1 to R7, as illustrated in FIG. 1, a problem may arise since sufficient voltages may not be charged in the pixels within the required period of time, e.g., one horizontal period.